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Altera_Forum
Honored Contributor
Honored ContributorPLL on DE2-70
Hello I was wondering if there were any good simple examples for using the PLLs on the DE2-70 written in Verilog. I was also wondering what the max clk rate is that can be generated from the PLL's us...
Altera_ForumHonored Contributor
Honored ContributorApart from Cyclone II Hardware Handbook, the altpll megafunction userguide provides a complete documentation of PLL configuration options. I suggest to use the Quartus MegaWizard to create your Verilog code. The maximum clk rate mainly depends on the IO standard of the respective outputs, for internal clocks, about 400 MHz can be achieved, but I'm not aware of C II speed grade utilized with DE2-70. See the C II Hardware manula for details.
