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It is generally a good practice to use asynchronous reset as shown below:
process(clock,reset)
variable p,i,result: signed(pi_o'range);
begin
if(reset = '1') then
i := (others => '0');
elsif rising_edge(clock) then
.......
end if;
end process;
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THis is only true IF you asynchronous reset is de-asserted synchronously. There is nothing wrong with sync resets - but in altera land sync resets are emulated in the fabric and can hurt timing in high speed applications, but it is much safer overall to use sync resets. In Xilinx async, resets should be avoided as much as possible.
So as a general rule, avoid async resets - sync resets are much safer.
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It is generally not a good practice to use variables unless your timing requirement is such that you cannot spare any clock cycle for the calculation.
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What a load of rubbish. Instead of trying to separate variables/signals, you need to understand the underlying logic. There is NOTHING you can do with variables you cant do with signals with regards RTL description. But there are plenty of things variables can do that you cant do with signals, but this is really just in simulation land.
As a beginner, NEVER use variables.
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