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Altera_Forum
Honored Contributor
16 years agoPart V-Lab Exercise 1
So after reading Part V like a few times,i fairly understand what does this examples wants me to do,and from the VHDL code given,i manage to get HEX0 going. One problem is the statement of "you...
Altera_Forum
Honored Contributor
16 years agoLooks like changing my MUXes around was one way of solving the problem. You'll notice that the vector ranges of the MUX inputs all shift. Take a good look at this version and my last version posted. When changing the MUX selectors, nothing changes, cause all of them output the same thing in all situations, until the shifting was done. I knew i had to shift something, just wasn't sure where to do it. NOW I CAN GET SOME SLEEP XD. on to part VI tomorrow morning(well, later this morning).
Mux0: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(14 DOWNTO 12), SW(11 DOWNTO 9),
SW(8 DOWNTO 6), SW(5 DOWNTO 3), SW(2 DOWNTO 0), M0);
Mux1: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(11 DOWNTO 9), SW(8 DOWNTO 6),
SW(5 DOWNTO 3), SW(2 DOWNTO 0), SW(14 DOWNTO 12), M1);
Mux2: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(8 DOWNTO 6), SW(5 DOWNTO 3),
SW(2 DOWNTO 0), SW(14 DOWNTO 12), SW(11 DOWNTO 9), M2);
Mux3: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(5 DOWNTO 3), SW(2 DOWNTO 0),
SW(14 DOWNTO 12), SW(11 DOWNTO 9), SW(8 DOWNTO 6), M3);
Mux4: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(2 DOWNTO 0), SW(14 DOWNTO 12),
SW(11 DOWNTO 9), SW(8 DOWNTO 6), SW(5 DOWNTO 3), M4); -edit- sorry about the formatting, it does look better in the code editor.