Part V-Lab Exercise 1

Hello,

Our lab instructions seem to be similar, with the only difference being that the bitwidths for our MUXes and the ammount of 7Segs we're using are different.

In the lab I am taking, I am told that I need to use boolean logic gates to do EVERYTHING tough. If i could use switches or if statements, I'd have been on to the next lab days ago!!! :D

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One problem is the statement of "you will need to use three instances of each of the subcircuits".What does this mean?Do i create 3 different VHDL codes and compiled to 1 like c++? or do i do everything in one page?

I am pretty confused with the code in BOLD given in the script.Could anyone explain to me what does it really mean?

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No, you make instances of the modules that you've created in previous previous parts 3 and 4. The code in bold are actually representations of those instances. Look at my version of the top level design to see an example.

Now where I'm lost is, that I don't know how to make the MUXes scroll the text!! PLEASE HELP!! :confused:

top level - part 5

ARCHITECTURE Behavior OF Lab1_5 IS
	COMPONENT Lab1_3
		PORT ( S, U, V, W, X, Y : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			   M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
	END COMPONENT;
	
	COMPONENT Lab1_4
		PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			   Display : OUT STD_LOGIC_VECTOR(0 TO 6));
	END COMPONENT;
	
	SIGNAL M0 : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL M1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL M2 : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL M3 : STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL M4 : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
	Mux0: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(14 DOWNTO 12), SW(14 DOWNTO 12),
						   SW(14 DOWNTO 12), SW(14 DOWNTO 12), SW(14 DOWNTO 12), M0);
	Mux1: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(11 DOWNTO 9),  SW(11 DOWNTO 9),
						   SW(11 DOWNTO 9),  SW(11 DOWNTO 9),  SW(11 DOWNTO 9), M1);
	Mux2: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(8 DOWNTO 6),   SW(8 DOWNTO 6),
						   SW(8 DOWNTO 6),   SW(8 DOWNTO 6),   SW(8 DOWNTO 6), M2);
	Mux3: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(5 DOWNTO 3),   SW(5 DOWNTO 3),
						   SW(5 DOWNTO 3), 	 SW(5 DOWNTO 3),   SW(5 DOWNTO 3), M3);
	Mux4: Lab1_3 PORT MAP (SW(17 DOWNTO 15), SW(2 DOWNTO 0),   SW(2 DOWNTO 0),
						   SW(2 DOWNTO 0), 	 SW(2 DOWNTO 0),   SW(2 DOWNTO 0), M4);
	
	H0: Lab1_4 PORT MAP (M0, HEX0);
	H1: Lab1_4 PORT MAP (M1, HEX1);
	H2: Lab1_4 PORT MAP (M2, HEX2);
	H3: Lab1_4 PORT MAP (M3, HEX3);
	H4: Lab1_4 PORT MAP (M4, HEX4);
	
END Behavior;

mux - lab 3

library ieee;
use ieee.std_logic_1164.all;
entity lab1_3 is
	port(S,U,V,W,
		 X,Y		: in std_logic_vector(2 downto 0);
		 M			: out std_logic_vector(2 downto 0)
	);
end lab1_3;
architecture behavioral of lab1_3 is
		
	signal uvm, wxm, uvwxm : std_logic_vector(2 downto 0);	
	
begin	
	uvm <= ((not (S(0) & S(0) & S(0))) and u) or ((S(0) & S(0) & S(0)) and v);
	
	wxm <= ((not (S(0) & S(0) & S(0))) and w) or ((S(0) & S(0) & S(0)) and x);
	
	uvwxm <= ((not (S(1) & S(1) & S(1))) and uvm) or ((S(1) & S(1) & S(1)) and wxm);
	
	M <= ((not (S(2) & S(2) & S(2))) and uvwxm) or ((S(2) & S(2) & S(2)) and y);
end behavioral;

7segs - lab 4

library ieee;
use ieee.std_logic_1164.all;
entity lab1_4 is
	port(C			: in std_logic_vector(2 downto 0); 
		 Display	: out std_logic_vector(0 to 6)
	);
end lab1_4;
architecture behavioral of lab1_4 is	
begin	
	Display(0) <= ((not C(2)) and (not C(1)) and (not C(0))) or 
			   ((not C(2)) and 	(C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));      
	
	Display(1) <= ((not C(2)) and (not C(1)) and 	(C(0))) or
			   ((not C(2)) and 	(C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0))); 
	
	Display(2) <= ((not C(2)) and (not C(1)) and 	(C(0))) or
			   ((not C(2)) and 	(C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));
	
	Display(3) <= ((not C(2)) and (not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));
	
	Display(4) <= ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));
			   
	Display(5) <= ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));
			   		   
	Display(6) <= ((not C(2)) and 	(C(1)) and (not C(0))) or
			   ((not C(2)) and 	(C(1)) and 	(C(0))) or
			   ((C(2)) and 	(not C(1)) and (not C(0))) or
			   ((C(2)) and 	(not C(1)) and 	(C(0))) or
			   ((C(2)) and 		(C(1)) and (not C(0))) or
			   ((C(2)) and 		(C(1)) and 	(C(0)));
			   
			   
end behavioral;