New Contributor
Regular ContributorHi,
May I know the status? Have you resolved the first error with the HDL code I have attached earlier?
For the second question, you may refer to a video published by Intel FPGA: Verilog HDL Basics
https://www.youtube.com/watch?v=PJGvZSlsLKs. The video shows how to implement behavioural statement at 31:02mins.
Thanks.
New Contributorthe program i came up with is:
module booth (mpr, mpd, prod, start, done, clk);
input [31:0] mpr, mpd;
input start, clk;
output [63:0] prod;
output done;
integer i;
reg [31:0] A, Q, M;
reg Q_1;
reg [5:0] count;
initial
begin
A <= 32'b0;
M <= mpd;
Q <= mpr;
Q_1 <= 1'b0;
count <= 6'b100000;
end
always@(negedge clk)
begin
case ({Q[0], Q_1})
2'b00 : {A, Q, Q_1}=A<<<Q<<<Q_1;
2'b01 : begin
A=A+M;
{A, Q, Q_1}=A<<<Q<<<Q_1;
end
2'b10 : begin
A=A-M;
{A, Q, Q_1}=A<<<Q<<<Q_1;
end
2'b11:{A, Q, Q_1}=A<<<Q<<<Q_1;
endcase
count=count-1'b1;
end
assign prod = {A, Q};
assign done = (count==0);
endmodule
no compilation errors but not working for these test cases:
Compilation : Passed
Test Case 1
0
Pass: (start = 1, mpr = 16, mpd = 10) => (clock cycles = 37, prod = 160, done = 1)\n
Fail: (start = 1, mpr = 16, mpd = 10) => (clock cycles = 37, prod != X, done != 0)\n
Wrong Answer
Test Case 2
1
Pass: (start = 0, mpr = 16, mpd = 10) => (clock cycles = 37, prod = x, done = x)\n
Fail: (start = 0, mpr = 16, mpd = 10) => (clock cycles = 37, prod != X, done != 0)\n
Wrong Answer
Test Case 3
2
Pass: (start = 1, mpr = 75, mpd = 20) => (clock cycles = 41, prod = 1500, done = 1)\n
Fail: (start = 1, mpr = 75, mpd = 20) => (clock cycles = 41, prod != X, done != 0)\n
Wrong Answer
Test Case 4
3
Pass: (start = 1, mpr = 85, mpd = 60) => (clock cycles = 43, prod = 5100, done = 1)\n
Fail: (start = 1, mpr = 85, mpd = 60) => (clock cycles = 43, prod != X, done != 0)\n
Wrong Answer
