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AManj1
New Contributor
New Contributorparity checker with reset
my program is: module detector (s_out, s_in, reset, clk); input s_in, reset, clk; output s_out; reg s_out; reg state; parameter even=0,odd=1; always@(posedge clk or reset) begin ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
May I know the status? Have you resolved the first error with the HDL code I have attached earlier?
For the second question, you may refer to a video published by Intel FPGA: Verilog HDL Basics
https://www.youtube.com/watch?v=PJGvZSlsLKs. The video shows how to implement behavioural statement at 31:02mins.
Thanks.
AManj1New Contributor
New Contributoryes the issue was resolved.
Thank you.
