Forum Discussion
AManj1
New Contributor
New Contributorparity checker with reset
my program is: module detector (s_out, s_in, reset, clk); input s_in, reset, clk; output s_out; reg s_out; reg state; parameter even=0,odd=1; always@(posedge clk or reset) begin ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorSure.
AManj1New Contributor
New Contributormodule detector (s_out, s_in, reset, clk);
input s_in, reset, clk;
output s_out;
parameter EVEN=1'b0, ODD=1'b1;
reg s_out, state;
always @(posedge clk, reset)
begin
if (!reset)
state <= EVEN;
else begin
case ({state,s_in})
2'b00,2'b11: begin
s_out <= 1'b0;
state <= EVEN;
end
2'b01,2'b10: begin
s_out <= 1'b1;
state <= ODD;
end
endcase
end
end
endmodule
allthough i think its the same program in a different way!!!!!!
