parity checker with reset

module detector (s_out, s_in, reset, clk);

input s_in, reset, clk;

output s_out;

parameter EVEN=1'b0, ODD=1'b1;

reg s_out, state;

always @(posedge clk, reset)

begin

if (!reset)

state <= EVEN;

else begin

case ({state,s_in})

2'b00,2'b11: begin

s_out <= 1'b0;

state <= EVEN;

end

2'b01,2'b10: begin

s_out <= 1'b1;

state <= ODD;

end

endcase

end

end

endmodule

allthough i think its the same program in a different way!!!!!!

any idea on how to implement this program?

Write a Verilog module to implement a 32-bit Booth’s multiplier using behavioural style. The module will take two 32-bit multiplier (“mpr”) and multiplicand (“mpd”) as inputs, and produce a 64-bit product (“prod”) as output. An active high input signal “start” is used to start the multiplication, and after completion of the multiplication, a signal “done” will be set to 1.and carry out the tasks at any individual stage including state transition in the failing edge of an input clock “clk”.

The following module template must be used for implementation:

module booth (mpr, mpd, prod, start, done, clk);

input [31:0] mpr, mpd;

input start, clk;

output [63:0] prod;

output done;