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AManj1
New Contributor
New Contributorparity checker with reset
my program is: module detector (s_out, s_in, reset, clk); input s_in, reset, clk; output s_out; reg s_out; reg state; parameter even=0,odd=1; always@(posedge clk or reset) begin ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
In an Event Control in the HDL, you specified an Event Control that contains both double-edge events and single-edge events. You cannot include both event types in one Event Control.
always@(posedge clk or reset)
I edited the HDL and the simulation result is correct.
Thanks.
KhaiChein_Y_IntelRegular Contributor
Regular Contributorposted a file.
