parity checker with reset

the program question is:

It is required to implement a sequence detector that will accept a serial bit stream “s_in” in synchronism with the positive edge of a clock, and will generate a serial bit stream “s_out” as output. The next bit of “s_out” will be 1, if the number of 1’s in “s_in” seen so far is odd; it will be 0 otherwise. The state transition diagram will consist of two states indicating whether the number of 1’s seen so far is odd or even. A “reset” low signal is used to asynchronously initialize the state to the “even 1’s state”.

my program:

module detector (s_out, s_in, reset, clk);

input s_in, reset, clk;

output s_out;

reg s_out;

reg state;

parameter even=0,odd=1;

always@(posedge clk or reset)

begin

if(!reset)

state<=even;

else

case(state)

0:begin

state<=s_in?odd:even;

s_out<=s_in?1:0;

end

1:begin

state<=s_in?even:odd;

s_out<=s_in?0:1;

end

default:state<=even;

endcase

end

endmodule

result of testcases:

Compilation : Passed

Public Test Cases: 1 / 4

Test Case 1

Pass: (state = x, s_in = 0, reset = 0) => (state = 0, s_out = x, reset = 0)\n

Pass: (state = x, s_in = 0, reset = 0) => (state = 0, s_out = x, reset = 0)\n

Passed

Test Case 2

Pass: (state = 0, s_in = 1, reset = 1) => (state = 1, s_out = 1, reset = 1)\n

Fail: (state = x, s_in = 1, reset = 1) => (state != 0, s_out != x, reset != 1)\n

Wrong Answer

Test Case 3

Pass: (state = 1, s_in = 1, reset = 1) => (state = 0, s_out = 0, reset = 1)\n

Fail: (state = 0, s_in = 1, reset = 1) => (state != 1, s_out != 1, reset != 1)\n

Wrong Answer

Test Case 4

Pass: (state = 1, s_in = 0, reset = 1) => (state = 1, s_out = 1, reset = 1)\n

Fail: (state = 0, s_in = 0, reset = 1) => (state != 0, s_out != 0, reset != 1)\n

Wrong Answer