Parallel Counter Block Diagram File Problem

Thanks for your reply. I, too. was surprised by this result, and am still not sure that this is entirely resolved even though I can't replicate it now. I've sometimes seen some wiring issues with unintentionally connected nets, but I did try deleting segments and re-routing this before posting the original comment and didn't see any change. I will pursue it on other designs.

I'd agree that a propagation delay issue is the logical answer, but couldn't see it in the simulation. With the reset to 0000 occurring where it did in the faulted circuit (e.g. counter clears when changing from 0111 to 1000 instead of continuing), that would suggest that the counter MSB changed from 0 to 1 happened before the LSB changed from 1 to 0 (and that both were present and stable enough at the time of the clock pulse to enable the clear through the NAND gate connected to the FF clear lines). The AND gate delay for changing the MSB to toggle mode would seem, if present, to put that change behind the LSB, which is in toggle mode all of the time, and all 4 FF's are clocked in parallel. I'd also have expected to see similar problems using other FF outputs to the NAND gate to shorten the count sequence for other MOD-number counters (e.g. MOD-12, etc.), and that didn't occur, so it is still somewhat of a mystery. I am wondering if the programming file somehow didn't get updated properly, but aren't those files generated anew each time that the compilation process takes place?