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Bobd's avatar
Bobd
Icon for New Contributor rankNew Contributor
5 years ago

Parallel Counter Block Diagram File Problem

When creating a 4-bit parallel counter block diagram file with shortened sequence (mod 10 decade) using Quartus Prime Lite 18.0 (see attached), have found what seems to be an inconsistent behavior. U...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

I don't think it is a schematic problem since the simulation is fine.

Have you checked whether the design pass timing?
Try to debug design by using Signal Tap to check whether the waveform is correct.