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Altera_Forum
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16 years ago

my SDRAM takes 14 clock cycles to read data !

i'm using the sdram on the altera de2 board i've connected a master component to the avalon-MM, that's supposed to perform reads from a slave (sdram controller) connected as well to the avalon bus...
Altera_Forum's avatar
Altera_Forum
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16 years ago

When using SDRAM make sure to post many back-to-back sequential accesses to increase the efficiency. If you were to post 8 back to back reads (like the Nios II cache for example) then there will be a long latency of 14 cycles and then best case eight back to back cycles of valid read data. Like Jacob said, caches exist for this reason because they are designed to post many sequential accesses any time a flush/line miss occurs.

This document should have diagrams showing what I just said: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf