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Altera_Forum
Honored Contributor
Honored Contributormy SDRAM takes 14 clock cycles to read data !
i'm using the sdram on the altera de2 board i've connected a master component to the avalon-MM, that's supposed to perform reads from a slave (sdram controller) connected as well to the avalon bus...
Altera_ForumHonored Contributor
Honored Contributorthanks for your replies ... after reading the sdram datasheet it seems that it's normal due to so many latency parameters, so it' about 5 clock cyles to read 16 bits and then so as to read 32 bits we will need to a double time : 10 clock cycles, the avalon bus should perform 2 successive reads making the full read operation more late ...
