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Altera_Forum's avatar
Altera_Forum
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16 years ago

my SDRAM takes 14 clock cycles to read data !

i'm using the sdram on the altera de2 board i've connected a master component to the avalon-MM, that's supposed to perform reads from a slave (sdram controller) connected as well to the avalon bus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I working with the same and it is ok with me.

You can send me your whole project and I will review it for you?

Please, zip your whole project.