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Altera_Forum's avatar
Altera_Forum
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16 years ago

my SDRAM takes 14 clock cycles to read data !

i'm using the sdram on the altera de2 board i've connected a master component to the avalon-MM, that's supposed to perform reads from a slave (sdram controller) connected as well to the avalon bus...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I don't have specific experience with the regular SDRAM controller. One of the big disadvantages to SDRAM (SDR,DDR,DDR2,DDR3) is the long read latency. SDRAM memory is horribly inefficient for single transactions. That is why processors all have instruction and data caches. The hope is that the cache will access large chunks of memory from the SDRAM and mask as much of the memory inefficiency as possible.

Have a look at page 57 of this SDRAM datasheet:

http://download.micron.com/pdf/datasheets/dram/sdram/512mbsdram.pdf

You see how many clock cycles it actually takes to execute a single READ command. Add on top of this any latencies added by the controller. A WRITE is easy, you just give the data to the controller and forget about it.

14 cycles is probably a worst case. I expect it gets more efficient under most normal circumstances.

Jake