My clock design is giving me an undefined output

Hello,

If you want a clock that can be used in a testbench, and that does work properly you can use someting link this (file.VHD):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
entity DE10_STD_CLK_BENCH is
end entity; 
 
 
architecture arch_DE10_STD_CLK_BENCH of DE10_STD_CLK_BENCH is 
 
constant F_Clock   : real :=50000000.0;
 
signal  T_CLK      : time     :=1.0/F_Clock * 1sec;
signal  CLOCK_50  : std_logic:='0';
 
begin
	main_clock: process 
	begin
		CLOCK_50<='1' after T_CLK / 2, '0' after T_CLK;
		wait until CLOCK_50='0';		
	end process;
END architecture;

Best Regards,

Johi.