Forum Discussion

MAlha's avatar
MAlha
Icon for New Contributor rankNew Contributor
7 years ago

My clock design is giving me an undefined output

Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
MAlha's avatar
MAlha
Icon for New Contributor rankNew Contributor
7 years ago

Hi,

I'm still eager to solve this issue so that I can progress forward with my project. Any help is appreciated.

How can I measure the period of one clock cycle in the above situation so that I'll be able to manually control it with my delay elements?

Thank you in advance,

Best regards.