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MAlha's avatar
MAlha
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7 years ago

My clock design is giving me an undefined output

Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
MAlha's avatar
MAlha
Icon for New Contributor rankNew Contributor
7 years ago

So I replaced the long chain of inverters with a long chain of LCELL primitives, and the tech. viewer is showing them correctly without washing them away, when I implement the design on hardware, and enable the Clk_en input, the LED lights up fadely, does this mean that the clock is working but oscillating too fast for the eye? If so then how do I measure the period of one clock cycle?

Thank you in advance,

Regards.