Forum Discussion
MAlha
New Contributor
New ContributorMy clock design is giving me an undefined output
Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
Lawrence_L_Intel
Occasional Contributor
Occasional ContributorHere is a thread that discusses this: https://forums.intel.com/s/question/0D50P00003yyP6gSAE/how-to-turn-off-the-optimization-that-removes-repeated-logic
Let us know how that works!
