Forum Discussion
MAlha
New Contributor
New ContributorMy clock design is giving me an undefined output
Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
MAlhaNew Contributor
New ContributorI did your suggestion, below are about 120 inverters:
But the compiler is washing them away:
How can I prevent that from happening so that I can implement it on hardware?
