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MAlha's avatar
MAlha
Icon for New Contributor rankNew Contributor
7 years ago

My clock design is giving me an undefined output

Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
Lawrence_L_Intel's avatar
Lawrence_L_Intel
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

The simulator doesn't take into gate delays so it won't model the oscillation that is based on the gate delay. When running this in hardware - trying stringing many inverters (100?) in a row so that the circuit has a chance to meet the VIH/VIL switching threshold. Make sure the compiler doesn't gobble up all the delay (check the fit report) on how many LUTs is uses.