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MAlha's avatar
MAlha
Icon for New Contributor rankNew Contributor
7 years ago

My clock design is giving me an undefined output

Greetings, I'm trying to implement a simple clock generator design using Quartus II web version 11.1: However when I configured it onto my Cyclone II DE2 FPGA, it gave me a 0 output when I se...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Can you check by varying 'Clk_en' input?

Instead of keeping it up high.

what exactly are you trying to do?

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)