MAX 10 LVDS serdes CDR

Hello,

This is Doosoo Ha, senior engineer of Opticis.

I am designing a LVDS serdes system using two(2) of MAX 10 devices.

I plan to build LVDS serdes system as transmitting data with only one LVDS signal line.

The LVDS using in my system is "LVDS with embedded clock". In other words, a separate clock signal for LVDS deserialization is not transmitted. I set LVDS serialize as factor is ‘10’ and the data rate as ‘100Mbps’.

I confirmed LVDS output is normal when inputting K28.5 data to LVDS serialize block.

After that, I designed deserialize block to LVDS deserialize block but problem has occurred during its verification.

What it saying as a problem is that the clock was asynchronized during deserialization because it was designed with "without clock signal".

I would like to know if there is any way clock not being asynchronized when I use LVDS with embedded clock without transmitting a separate clock signal for LVDS deserialization.

Please assist me how I can solve this problem.