New Contributor
Regular ContributorHi,
If you look into stp2.stp file, I observed that the avmm_data_write signal is high very long. Is this expected as I expect it to be high for only 1 clock cycle only?
From your testing, it looks like most of the time you are facing data written incorrectly. This means that there is a timing violation where the data might be corrupted due to not handling the data correctly. Have you check your timing analysis to see if there is any timing violation? Are you able to make the changes on your code so that you state machine is more stable when performing write and read?
