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Altera_Forum
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14 years ago

Laboratory exercise 3: Part V [Verilog]

Hi there! I am looking for some help or hints with Lab3 part V. I've done all the previous exercise, but I can't get any grip on that one. I've written a module which is convert a for bit b...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

that should work.. i hope you realized that your circuit is level triggered and not edge triggered.. a 16 bit edge triggered d flip flop would look like this 


module D_latch_async_rst(RST, CLK, DAT, Q);     
     input RST, CLK;
     input  DAT;
     output reg  Q;
     always @ (posedge CLK) begin
             if(~RST)
                  Q = 1'b0;
             else 
                  Q = DAT;
     end
endmodule

i hope someone will correct me if im wrong