Laboratory exercise 3: Part V [Verilog]

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what were you planning to achieve using the gated d latch?

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A circuit that can store a 16 binary number.

Something like this:

img132.imageshack.us/img132/7247/circx.png

But instead of 4 instances I would use 16 so I could store 16 bits.

~CLR would be KEY0

CLK would be ~KEY1

module D_latch_async_rst(RST, CLK, DAT, Q);
	input RST, CLK, DAT;
	output reg Q;
	
	always @ (RST or CLK or DAT)
		if(~RST)
			Q = 1'b0;
                else if (CLK)
                        Q = DAT;
endmodule