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Altera_Forum
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14 years ago

Laboratory exercise 3: Part V [Verilog]

Hi there! I am looking for some help or hints with Lab3 part V. I've done all the previous exercise, but I can't get any grip on that one. I've written a module which is convert a for bit b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

if you have a 16 bit register as the input 


reg  input_data;
reg  a,b,c,d;
you can access 4bit segments of it like 


a=input_data;
b=input_data;
c=input_data;
d=input_data;

a register itself is a latch. what were you planning to achieve using the gated d latch?