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could be a lot more helpful if you could post your laboratory question :)
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That is obvious. Sorry. So here's the instructions from Lab3 Part V:
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Part V
We wish to display the hexadecimal value of a 16-bit number A on the four 7-segment displays, HEX7-4. We
also wish to display the hex value of a 16-bit number B on the four 7-segment displays, HEX3-0. The values
of A and B are inputs to the circuit which are provided by means of switches SW15-0. This is to be done by first
setting the switches to the value of A and then setting the switches to the value of B; therefore, the value of A
must be stored in the circuit.
1. Create a new Quartus II project which will be used to implement the desired circuit on the Altera DE2-series
board.
2. Write a Verilog file that provides the necessary functionality. Use KEY0 as an active-low asynchronous
reset, and use KEY1 as a clock input.
3. Include the Verilog file in your project and compile the circuit.
4. Assign the pins on the FPGA to connect to the switches and 7-segment displays, as indicated in the User
Manual for the DE2-series board.
5. Recompile the circuit and download it into the FPGA chip.
6. Test the functionality of your design by toggling the switches and observing the output displays.
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This is the module that I mentioned above:
module _7_seg(S, H);
input S;
output H;
assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (S&~S&S&S) | (S&S&~S&S);
assign H = (~S&S&~S&S) | (~S&S&S&~S) | (S&~S&S&S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S);
assign H = (~S&~S&S&~S) | (S&S&~S&~S) | (S&S&S&~S) | (S&S&S&S);
assign H = (~S&~S&~S&S) | (~S&S&~S&~S) | (~S&S&S&S) | (S&~S&S&~S) | (S&S&S&S);
assign H = (~S&~S&~S&S) | (~S&~S&S&S) | (~S&S&~S&~S) | (~S&S&~S&S) | (~S&S&S&S) | (S&~S&~S&S);
assign H = (~S&~S&~S&S) | (~S&~S&S&~S) | (~S&~S&S&S) | (~S&S&S&S) | (S&S&~S&S);
assign H = (~S&~S&~S&~S) | (~S&~S&~S&S) | (~S&S&S&S) | (S&S&~S&~S);
endmodule
It converts a 4 bit binary into a single digit hexa, which can be displayed on the 7 seg display.
I guess I should use 16 inscances of a
gated d latch, somethig like this:
module gated_D_latch(Clk, D, Q);
input Clk, D;
output Q;
wire S, R, R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign S = D;
assign R = ~D;
assign S_g = ~(S & Clk);
assign R_g = ~(Clk & R);
assign Qa = ~(S_g & Qb);
assign Qb = ~(Qa & R_g);
assign Q = Qa;
endmodule
All instances using the same Clk. But I don't know how should I wire this components up?
Honored Contributor
