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Altera_Forum
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14 years ago

Laboratory exercise 3: Part V [Verilog]

Hi there! I am looking for some help or hints with Lab3 part V. I've done all the previous exercise, but I can't get any grip on that one. I've written a module which is convert a for bit b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

could be a lot more helpful if you could post your laboratory question :)