Forum Discussion
FvM
Super Contributor
1 year agoHi,
some issues with the code
- bit_cnt == 8 (else condition) does never happen, need reg [3:0] bit_cnt;
- data_reg is only loaded once on POR, spi_master sends mosi == 0 constantly after first frame
- using always @(posedge sclk) is legal but might cause timing issues in a complexer design. Better use single system clock and modify
clock-enable scheme respectively
What's the indended SPI mode?
Regards
Frank