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I'm teaching techniques to cross clock domains (CDC), and I need to develop some demonstrators.
For some techniques, you would cascade D-Type FlipFlops without any combinational logic between them. These D-Types also need to be as close as possible, and have the fastest setup time possible of course.
We are using a Cyclone IV on a DE0-Nano board, but I assume the issue is the same for the DE1 boards (which we will move to next year)
It's straightforward to write VHDL to build a clock synchroniser. The issues I am uncertain about is how to constrain the synthesis to minimise mtbf.
Maybe there is a standard component that allows me to build a clock synchroniser? (I could not find one).
Many thanks in advance.
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I wire two registers directly...and leave it to tool. The ideal is balanced setup/hold rather than best setup.
You may therefore add max/min delay on that path to target balanced timing but I never done that.
you also need false path at cross over.
dual clock fifos sdc may give better details.
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