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Altera_Forum
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17 years ago

Implementation of Digital PID controller in FPGA

I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation, c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki...
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Altera_Forum
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17 years ago

Hi POWERGUI

To sum up, I hope the following method will work:

(we only need saturation if there is feedback. If there is no feedback then we can accommodate the result).

Assume adder inputs are x1, x2 each 8 bits 2's complement and adder result is S of 9 bits. for feedback x2 = S(8) & S(6:0). i.e. discard S(7). This brings us back to the concept of MSB discarding algorithm, thus:

if S(7) is opposite S(8) then fill up all S(or x2) with opposite of S(8).