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Altera_Forum
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17 years ago

Implementation of Digital PID controller in FPGA

I'm trying to implement a PI controller in FPGA using schematic entry method in altera quartus II . I'm using the following equivalent PI controller equation, c(n) = c(n-1)+kp*(e(n)-e(n-1))+Ki...
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Altera_Forum
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17 years ago

Hi FvM,

Thanks for the clarification, I agree totally that in cases of feedback overflow will occur and be fatal. This saturation is different from my clipping. We better say overflow protection.

Apologies, I can see now what your function is doing, in effect precomputing to prevent overflow. it seems like DSP Vs control systems conflict.