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Also noticed that The two dff on the top left(inst1 and inst2) are 16 bit but should be 8bit. When I double click them, the megawizard shows them as 16 bit. Not sure if this is a problem.
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The width is automaticly set to 8 in compilation, even without causing a warning. This is a special feature of schematic entry evaluation, I think. It also infers a multi-bit register from a single bit one.
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But when I tried to simulate the schematic with the corrections you mentioned with a waveform file, I got correct result for 2 periods only.
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I see, that your simulation output has 8 bit. I don't understand what you connected here, cause your design has a 16-bit output.
Generally I see two problems. Controller deviation signal e is by it's nature of SIGNED type, no matter what your input signals are. To my opinion it's advisable, to use SIGNED for all signals throughout a PI controller, also for coefficients to avoid type confusion.
The
output stuck to ground refers to a problem of coefficient scaling and required signal widths in your design. I already mentioned the need to limit the integrator output. These points are not related to FPGA programming rather than basic DSP issues. They also arise with digital microprocessor controllers and can be examined (and solved) by pencil and paper methods.
P.S.: As another supplement: Cause the sampling period T most likely is a multiple of the system clock period, the delaying FFs should have a clock enable to set the sampling period.
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