Implementation of Digital PID controller in FPGA

gmpstr,

Thanks a lot for response. I used D type flip flop and I sucessfully implemented

kp*(e(n)-e(n-1))+Ki*T*e(n-1)

but once I took the c(n) and pass it through D type flip flop to get c(n-1) and add to above, my problem started. The value of c(n-1) is always zero though it acutally is not and the result is just always equal to

kp*(e(n)-e(n-1))+Ki*T*e(n-1).

During synthesis, I got the following warning,

Warning (14130): Reduced register "lpm_dff0:inst9|lpm_ff:lpm_ff_component|dffs[0]" with stuck data_in port to stuck value GND

Warning: Output pins are stuck at VCC or GND

Warning (13410): Pin "output[0]" is stuck at GND

Maybe this will help you understand my problem. I hope to get feedback from you in this matter.