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HBin0's avatar
HBin0
Icon for New Contributor rankNew Contributor
6 years ago

I use DSP Builder in Quartus Prime Pro 19.4, When I setup generate hardware option in CONTROL BLOCK， run simulink simulation ， failure is reported

Error reported by S-function 'mip_control' in 'lms/Control': Failure to redistribute delay in [lms_Subsystem] - negative cycle (0) Sub | lms_Subsystem | { } (0) Add_PostCast_primWireOut_sel_x | l...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

I have received valid response from Factory. As I understand it, Factory has looked into your design and commented that your subsystem contains a loop with 3 Mult blocks and only 1 Sample Delay of depth=1. Each Mult block has 2 registers irrespective of clock frequency, so you need to have at least depth=6 Sample Delay in that loop.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin