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HBin0's avatar
HBin0
Icon for New Contributor rankNew Contributor
5 years ago

I use DSP Builder in Quartus Prime Pro 19.4, When I setup generate hardware option in CONTROL BLOCK， run simulink simulation ， failure is reported

Error reported by S-function 'mip_control' in 'lms/Control': Failure to redistribute delay in [lms_Subsystem] - negative cycle (0) Sub | lms_Subsystem | { } (0) Add_PostCast_primWireOut_sel_x | l...
HBin0's avatar
HBin0
Icon for New Contributor rankNew Contributor
5 years ago

I advice you upload this design to factory， I this the engineer who design DSP Builder can find the reason of error， I estimate it is possible have design rule need to notice， not this design itself。 I think to let all people who use DSP builder know the reason it is most important ，not to try and try agian。

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago
Hi, Thanks for your update. Just would like to set a correct expectation. Generally Factory will only investigate into a confirmed bug but not potential design related issue. Just would like to check with you if you are seeing expected output from the Matlab simulation? If yes, then I can leverage this to explain to Factory that no issue with simulation and request for their help to look into why HDL generation encounter issue. Thank you very much. Best regards, Chee Pin