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HBin0's avatar
HBin0
Icon for New Contributor rankNew Contributor
5 years ago

I use DSP Builder in Quartus Prime Pro 19.4, When I setup generate hardware option in CONTROL BLOCK， run simulink simulation ， failure is reported

Error reported by S-function 'mip_control' in 'lms/Control': Failure to redistribute delay in [lms_Subsystem] - negative cycle (0) Sub | lms_Subsystem | { } (0) Add_PostCast_primWireOut_sel_x | l...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Sorry for the delay. I am able to open your design and replicate the error when running Simulink. As I perform further tests, the error seems to be related to your design or algorithm which could potentially cannot be synthesized. As I tested simplifying your subsystem to only simple subtraction, the RTL generation is passing. I am not really a design expert and could not really comment on what might be wrong with your design. You might need to further look into your subsystem and probably add portion by portion to see if can spot any anomaly.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin