Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorİnitialization Ram with VHDL
Hi, As you know, in Verilog, initialize $readmemh code is initialized Ram simply. I searched a VHDL code like this but i can't get. Do you help me to find this code? If you know a sample, can y...
Altera_ForumHonored Contributor
Honored Contributorthank you it is working fine (i think) just another questions can i write the resulte in a file like .mif using a RAM ?? if there is another way please tell me about it
thank's again .....
