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Altera_Forum's avatar
Altera_Forum
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15 years ago

İnitialization Ram with VHDL

Hi, As you know, in Verilog, initialize $readmemh code is initialized Ram simply. I searched a VHDL code like this but i can't get. Do you help me to find this code? If you know a sample, can y...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thank you it is working fine (i think) just another questions can i write the resulte in a file like .mif using a RAM ?? if there is another way please tell me about it

thank's again .....