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Altera_Forum
Honored Contributor
15 years agoİnitialization Ram with VHDL
Hi, As you know, in Verilog, initialize $readmemh code is initialized Ram simply. I searched a VHDL code like this but i can't get. Do you help me to find this code? If you know a sample, can y...
Altera_Forum
Honored Contributor
15 years agoHey
Can you help me, how can i use a .mif file to initialize a RAM, can you give me the steps to do in the programming phase with vhdl language ... or give me an exemple of that (how i should write) .... thank's in advance ........