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Altera_Forum
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15 years ago

İnitialization Ram with VHDL

Hi, As you know, in Verilog, initialize $readmemh code is initialized Ram simply. I searched a VHDL code like this but i can't get. Do you help me to find this code? If you know a sample, can y...
Altera_Forum's avatar
Altera_Forum
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15 years ago

If this is for simulation purpose, then initialize the memory content when u create them, but you need to use simulator like ModelSim

If this is an actual circuit then you MUST use mif file to initialize memory content. The programmer tool will initialize the memory when it programs the FPGA.