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Altera_Forum
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15 years ago

İnitialization Ram with VHDL

Hi, As you know, in Verilog, initialize $readmemh code is initialized Ram simply. I searched a VHDL code like this but i can't get. Do you help me to find this code? If you know a sample, can y...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In quartus, there are only 2 ways to initialise a ram using VHDL:

1. using a function to set all values.

2. Use a mif file in conjuntion with a megawizard generated altsyncram.

Annoyingly, you cannot use textio to read data in from a text file (like you can with verilog and X based FPGAs).