HPS FPGA UARTs Mapping Change

I presume you are using the A10 SDMMC boot, with GHRD design. In GHRD design, UART is configured with dedicated IO. You can ensure same UART node configuration in both U-Boot device tree and Linux device tree., and serial0 is specified.

Example UART node configuration at U-Boot DTS

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10_socdk.dtsi

aliases {

ethernet0 = &gmac0;

serial0 = &uart1;

i2c0 = &i2c1;

};

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10_socdk.dtsi

&uart1 {

u-boot,dm-pre-reloc;

status = "okay";

};

https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2019.10/arch/arm/dts/socfpga_arria10.dtsi

uart0: serial0@ffc02000 {

compatible = "snps,dw-apb-uart";

reg = <0xffc02000 0x100>;

interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;

reg-shift = <2>;

reg-io-width = <4>;

clocks = <&l4_sp_clk>;

resets = <&rst UART0_RESET>;

status = "disabled";

};

uart1: serial1@ffc02100 {

compatible = "snps,dw-apb-uart";

reg = <0xffc02100 0x100>;

interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;

reg-shift = <2>;

reg-io-width = <4>;

clocks = <&l4_sp_clk>;

resets = <&rst UART1_RESET>;

status = "disabled";

};