How to supress hierarchy optimizer for logic cells?

Hi Jerry!

The FPGA part number used was EP2C70F896C6.

Actually, by the documentation each lcell brings about 447ps delay.

I got the 4.25ns by simulation and oscilloscope :)

I had change a lot of things meanwhile and finished it about July/2011. My last code for the pulse delay module is this:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pd IS
	PORT
	(
		pulse 	:in std_logic;
		pulse_d	:out std_logic
	);
end pd;
architecture beha of pd is
	
-- N gives the pulse delay multiplier. pulse_delay = N*lcell_delay
-- N must be adjusted to be coherent to pulse_delay desired and lcell_delay of using device
-- logic cell delay can be found in device performance documentation
	constant N : integer := 17;
-- lcell array with N elements
	signal delay_line: std_logic_vector(N-1 downto 0);
-- these attributes force synthesizer to keep our buffer alone :)
-- this ensures that delay is the expected
	attribute keep: boolean;
	attribute keep of delay_line: signal is true;
	
	begin
	gen_delay:
	for i IN 1  TO N-1 generate
	delay_line(i) <= delay_line(i-1);
	end generate;
	delay_line(0) <= pulse;
	pulse_d <= delay_line(N-1);
end beha;

This is easier to change, as if you need more or less delay per instance you just need to increase or decrease, respectively, the constant N value.

The delay value will be N*lcell_delay.

Hope this can be helpful :)

Cheers,

Mateus