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Altera_Forum
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15 years ago

How to supress hierarchy optimizer for logic cells?

Hi all! :) I'm a newbie here and in FPGA trips...:rolleyes: I'm trying to make a signal delay using AND ports and I'm having some difficult... At start, I need to delay a signal ~10ns...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Another question is how did you get 4.25ns value? I mean did you find the value from the compliation report or measure it thru osciliscope?