How to supress hierarchy optimizer for logic cells?

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Is the 4.25ns delay stable over the whole temperature range? Is it an average/min/max value?

I'm not so sure you'll get an accurate delay with this method.

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I had no time to make all tests, but at ~18ºC of room temperature I used a spot light to increase board temperature and see no variation.

Do you know a better method?

I think I don't refer yet , but its for asynchronous delay.. I can´t use clock or pll signals to make it due to accuracy needed.

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I'm performing a several tests and optimization and i'll put here some results :)