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Altera_Forum
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14 years ago

How to supress hierarchy optimizer for logic cells?

Hi all! :) I'm a newbie here and in FPGA trips...:rolleyes: I'm trying to make a signal delay using AND ports and I'm having some difficult... At start, I need to delay a signal ~10ns...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Is the 4.25ns delay stable over the whole temperature range? Is it an average/min/max value?

I'm not so sure you'll get an accurate delay with this method.