How to supress hierarchy optimizer for logic cells?

Hey guys,

After many hours and some smoke out of my head, I find a solution and I let here for future reference.

1st place, I'm studying FPGA development about 1~2 months and I'm a beginner, don't believe in anything I say... :P

To create signal delay with a few ns, despite what we know of discrete logic circuits, it's not a good practice use logic gates in chain. Synthesizer will try to make some optimizations and will blow up all your work.

Most secure and strong (imho) way to do it is force signal route through logic cells. Delay time will be practically exact and multiple of# lcell that you use.

I made this module in verilog:

module pd (pulse,pulse_out);
input pulse;
output pulse_out;
wire a, b, c, d, f, g, h, i, j, k, l;
lcell lc1 (pulse,a);
lcell lc2 (a,b);
lcell lc3 (b,c);
lcell lc4 (c,d);
lcell lc5 (d,e);
lcell lc6 (e,f);
lcell lc7 (f,g);
lcell lc8 (g,h);
lcell lc9 (h,i);
lcell lc10 (i,j);
lcell lc11 (j,k);
lcell lc12 (k,l);
lcell lc13 (l,pulse_out);
endmodule

and use it in top-entry entity in VHDL:

    
...
COMPONENT pd
    PORT
    (
      pulse              :IN       STD_LOGIC;
      pulse_out        :OUT    STD_LOGIC
     );
END COMPONENT;
...
  PA0: pd PORT MAP (A, A1);
  PA1: pd PORT MAP (A1, A2);
  PA2: pd PORT MAP (A2, A3);
...

Each instance adds 4.25ns delay to signal (in DE2-70, others devices could be more or less).

Technology Map in my project shows that 6 instances of "pd" are implemented using only 2 lcells, much better that using logic gates.

that's the result:

general schematic

http://img576.imageshack.us/img576/9804/pulseshapping.png

and the lcell chain :-P

http://img204.imageshack.us/img204/6898/lcellchain.png

Hope it will be useful to more people :)