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Altera_Forum
Honored Contributor
Honored ContributorHow to supress hierarchy optimizer for logic cells?
Hi all! :) I'm a newbie here and in FPGA trips...:rolleyes: I'm trying to make a signal delay using AND ports and I'm having some difficult... At start, I need to delay a signal ~10ns...
Altera_ForumHonored Contributor
Honored ContributorI already have a answer but need 4 posts to include links, sorry the spam but it's for a good cause :P
